vishay siliconix sic734cd9 document number: 73672 s-62656?rev. c, 25-dec-06 www.vishay.com 1 fast switching mosfets with integrated driver features ? low-side mosfet control pin for pre-bias start-up ? undervoltage lockout for safe operation ? internal boostrap diode reduces component count ? break-before-make operation ? turn-on/turn-off capability ? compatible with any single or multi-phase pwm controller ? low profile, thermally enhanced powerpak ? mlf 9 x 9 package applications ? dc-to-dc point-of-load converters - 3.3 v, 5 v, or 12 v intermediate bus - examples - 12 v in /0.8 - 2.5 v out - 5 v in /0.8 - 1.5 v out ? servers and computers ? single and multi-phase conversion description the sic734cd9 is an integrated solution which contains two pwm-optimized mosfets (high side and low side mos- fets) and a driver ic. integratin g the driver allows better op- timization of power mosfets. this minimizes the losses and provides better performance at higher frequency. the sic734cd9 is packed in vishay siliconix?s high performance powerpak mlf 9 x 9 package. compact co-packing of com- ponents helps to reduce stray inductance, and hence in- creases efficiency. functional block diagram product summary input voltage range 3.3 to 24 v output voltage range 0.5 to 6 v operating frequency 100 khz to 1 mhz continuous output current up to 25 a peak efficiency 92.8 optimized duty cycle ratio 10 % powerpak mlf 9 x 9 bottom view ordering information: SIC734CD9-T1 figure 1. c boot v i n s w v dd p w m cg n d v dd u v lo pg n d bbm sy n c shd n + -
www.vishay.com 2 document number: 73672 s-62656?rev. c, 25-dec-06 vishay siliconix sic734cd9 stresses beyond those listed under "absol ute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. notes: a. see reliability manual for profile. the powerpak mlf 9 x 9 is a leadless package. the end of t he lead terminal is exposed co pper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the expo sed copper tip cannot guaranteed and is not required to ensure adequate bottom side soldering interconnection. b. rework conditions: manual solder ing with a soldering iron is not recommended for leadless components. c. junction-to-case thermal impedance represents the effective th ermal impedance of all heat carr ying leads in parallel and is intended for use in conjunction with the thermal impedance of the pc board pads to ambient (r thja = r thjc + r thpcb-a ). it can also be used to estimate chip temperature if power dissipation and the lead temper ature of heat carrying (drain) lead is known. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol steady state unit logic supply v dd 7 v logic inputs v pwm 7.3 common switch node v sw 30 drain voltage v in 30 bootstrap voltage c boot sw + 7 maximum power sissipation (measured at 25 c ) p d 6w operating juncyion and storage temperature range t j , t stg - 65 to 125 c soldering recommendations (peak temperature) a, b 225 recommended operating conditions parameter symbol steady state unit drain voltage v in 3.3 to 24 v logic supply v dd 4.5 to 5.5 input logic pwm voltage v pwm 5 bootstrap capacitor c boot 100 n to 1 f thermal resistance ratings parameter c symbol typical maximum unit maximum junction-to-case steady state r thjc 3.5 4.5 c/w maximum junction-to-ambient (pcb = copper 25 mm x 25 mm) r thja 60 75
document number: 73672 s-62656?rev. c, 25-dec-06 www.vishay.com 3 vishay siliconix sic734cd9 notes: a. pulse test; pulse width 300 ms, duty cycle 2 %. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. using application board sidb766706. specifications parameter symbol test conditions unless specified t a = 25 c 4.5 v < v dd < 5.5 v, 4.5 v < v in < 20 v limits unit min typ a max controller logic voltage v dd 4.5 5.5 v logic current (static) i dd(en) v dd = 4.5 v, sync = h, pwm = h, shdn = h 1185 a i dd(dis) v dd = 4.5 v, sync = h, pwm = h, shdn = l 115 logic current (dynamic) i dd1(dyn) v dd = 5 v, f pwm = 250 khz c 24 ma i dd2(dyn) v dd = 5 v, f pwm = 700 khz c 52 logic input logic input (vpwm) high v pwmh v dd = 5 v, sync = h, shdn = h 2.5 v low v pwml 1.35 logic input voltage (v sync )v sync v dd = 5 v, pmw = h, shdn = h 2.0 logic input voltage (v shdn )v shdn v dd = 5 v, pmw = h, sync = h 2.0 input voltage hysteresis (pwm) v hys 400 mv logic input current i shdn v dd = 5.5 v, shdn = 0 v 117 a i pwm v dd = 5.5 v, pmw = 5.5 v 114 protection break-before-make reference v bbm v dd = 5.5 v 2.4 v under-voltage lockout v uvlo v dd = 5 v, sync = h, shdn = h 3.5 4.1 4.25 under-voltage lockout hysteresis v h 0.4 mosfets drain-source voltage v ds i d = 250 a 30 32 v drain-source on-state resistance a r ds(on)1 v dd = 5 v, i d = 10 a high-side 9.5 12.3 m r ds(on)2 t a = 25 c low-side 3.7 4.5 diode forward voltage a v sd1 i s = 2 a, v gs = 0 v high-side 0.7 1.1 v v sd2 low-side 0.67 1.1 dynamic b, c tu r n o n d e l ay t i m e t d(on) 50 % - 50 % c 58 ns turn off delay time t d(off) 31
www.vishay.com 4 document number: 73672 s-62656?rev. c, 25-dec-06 vishay siliconix sic734cd9 timing diagram application information a (25 c, unless noted, lfm = 0) notes: a. experimental results using an evaluation board with a specific set of operating conditions. figure 2. shd n p w m s w t d(on) t d(off) sy n c hs mosfet gate ls mosfet gate figure 3. total efficiency 12 v in /1.3 v out 8 0 8 2 8 4 8 6 88 90 92 94 96 3 5 7 9 11 13 15 17 19 21 23 25 o u tp u t c u rrent ? (a) ) % ( y c n e i c i f f e 700 khz 500 khz 300 khz figure 4. total loss 12 v in /1.3 v out 0 1 2 3 4 5 6 7 3 5 7 9 11 13 15 17 19 21 23 25 ) w ( s s o l l a t o t o u tp u t c u rrent ? (a) 300 khz 500 khz 700 khz
document number: 73672 s-62656?rev. c, 25-dec-06 www.vishay.com 5 vishay siliconix sic734cd9 pin configuration d n g p c boot powerpak mlf 9 mm x 9 mm (bottom view) low-side mos tab (sw) high-side mos tab v in driver tab cgnd 1 v in 2 v in 3 v in 4 v in 5 cgnd 6 c boot 7 8 v dd 9 v d d 0 1 v d d 2 1 d n g c 3 1 c n y s 4 1 n d h s 5 1 d n g p 6 1 2 3 v n i 1 3 v n i 0 3 v n i 9 2 w s 8 2 w s 7 2 w s 6 2 w s 5 2 w s 24 pgnd 23 pgnd 22 pgnd 21 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 1 1 m w p truth table shdn sync pwm hs mosfet ls mosfet lxxoffoff hlloffoff hlhonoff hhloffon hhhonoff pin description pin number symbol description 1 - 4, 30 - 32 v in input-voltage (high-side mosfet drain) 5, 12 cgnd control ground. shoul d be connected to pgnd externally 6, 7 c boot connection pin for bootstrap c apacitor for high-side mosfet 8, 9, 10 v dd logic supply voltage - decoupling to g nd with a cap is strongly recommended 11 pmw pulse width modulation (pwm) signal input 13 sync disable low-side mosfet drive 14 shdn disable all functions (active low) 15 - 24 pgnd power ground (low-side mosfet source) 25 - 29 sw connection pin for output inductor (hi gh-side mosfet source/low-side mosfet drain)
www.vishay.com 6 document number: 73672 s-62656?rev. c, 25-dec-06 vishay siliconix sic734cd9 device operation pulse width modulator (pwm) this is a cmos compatible logic input that receives the drive signals from the controller circuit. the pwm signal drives the buck switch. break-before-make (bbm) the sic730cd9 has an intrenal break-before-make function to ensure that both high-side and low-side mosfets are not turned on the same time. the low-side mosfet will not turn on until the high-side gate dr ive voltage is less than v bbm , thus ensuring that the high-si de mosfet is turned off. this parameter is not user adjustable. shdn cmos logic signal. in the low state, the shdn disables both high-side and low-side mosfet?s. capacitor to boot input (c boot ) connected to v dd by an internal diode via the c boot pin, the boot capacitor is used to sust ain rail for the high-side mos- fet gate drive circuit. under voltage lockout (uvlo) during the start up cycle, the uv lo disables the gate drive holding high-side and low-side mosfet?s low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the uvlo is not user adjustable. sync pin for pre- bias start-up the low side mosfet can be individually enable or dis- abled by using the sync pin. in the low state (sync = low), the low-side mosfet is turned off. in the high state, the low-side mosfet is enabled and follows the pwm input signal (see timing diagram, figure 2). sync is a cmos compatible logic input and is used for a pre?biased output voltage. voltage input (v in ) this is the power input to the drain of the high-side power mosfet. this pin is connected to the high power intermedi- ate bus rail. switch node (sw) the switch node is the circuit pwm regulated output. this is the output applied to the filter circuit to deliver the regulated high output for the buck converter. power ground (pgnd) this is the output connection from the source of the low-side mosfet. this output is the gr ound return loop for the power rail. it should be externally connected to cgnd. control ground (cgnd) this is the control voltage return path for the driver and logic input circuitry to the sic730cd9. this should externally con- nected to pgnd. application circuit the sic734cd9 has a built-in delay time that is optimized for the mosfet pair. when the pwm signal goes low, the high- side driver will turn off, after circuit delay (t doff ), and the out- put will start to ramp down, (t f ). after a further delay, the low- side driver turns on. when the pwm goes high, the low-side driver turns off, (t don ). as the body diode starts to conduct, the high-side mosfet turns on after a short dalay. the delay is minimized to limit body diode conduction. the output then ramps up, (t r ). cgnd 5 v 3.3 v to 16 v mosfet drive circuitry with break-before- make c boot v in sw c boot l + pgnd cgnd shdn v dd q 1 q 2 dc-dc controller v out pwm sync power up sequence : the presence of v dd prior to applying the v in and pwm is recommended to ensure a safe turn on power down sequence: the sequence should be reverse of the on sequence, turn off the v in before turning off the v dd . pgnd hs ls figure 7 the sic714cd10 has a built-in delay time that is optimized for the mosfet pair. when the pwm signal goes low, the high-side driver will turn off, after circuit delay (t doff ), and the output will start to ramp down,(t f ). after a further delay, the low-side driver turns on. when the pwm goes high, the low-side driver turns off,(t don ). as the body diode starts to conduct, the high-side mosfet turns on after a short delay . the delay is minimized to limit body diode conduction. the output then ramps up,(t r ).
vishay siliconix sic734cd9 document number: 73672 s-62656?rev. c, 25-dec-06 www.vishay.com 7 typical application vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?73672. figure 8. v i n v dd sy n c shd n cg n d c boot s w pg n d p w m sic734cd9 v i n v dd sy n c shd n cg n d c boot s w pg n d p w m sic734cd9 v i n v dd sy n c shd n cg n d c boot s w pg n d p w m sic734cd9 v i n v dd sy n c shd n cg n d c boot s w pg n d p w m sic734cd9 v out p w m1 p w m2 p w m3 p w m4 p w m control circ u it 5 v 12 v
11 c l e terminal tip e c l cc odd t erminal side even t erminal side a1 b 4 section ?c ? c? scale: none notes: 1. die thickness allowable is 0.305-maximum (0.12-inches maximum) 2. dimensioning and tolerancing conform to asme y14.5m-1994. 3. n is the total number of terminals. nd is the number of terminals in the x-direction and ne is the number of terminals in th e y-direction. 4. dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 5. the pin #1 identifier must exist on the top surface of the package. the identifier may be an indentation mark or other featu re of the package body. 6. exact shape and size of this feature is optional. 7. millimeters will govern. 8. the shape shown on four corners are not actual i/o. 9. package warpage maximum is 0.08 mm. 10. applied for exposed pad and terminals exclude embedding part of exposed pad from measuring. 11. applied only for terminals. a d d/2 d1 d1/2 n c 0.10 2x a c 0.10 2x b 0.80 dia 5 6 1 2 3 e/2 e e1/2 e1 b top view c 0.10 2x b c 0.10 2x a seating plane c 0.08 10 a a1 a2 a3 c side view 4 p 4 p 0.45 0.25 min l 0.25 min e d4 (nd ? 1)xe ref. bottom view d4 d5 c 0.10 m a b 4 b d6 d2 d2/2 pin 1 id 0.20 r. n e2/2 e3 e4 e2 (ne ? 1)xe ref. d3 1 2 3 package information vishay siliconix document number: 73386 02-may-05 www.vishay.com 1 of 2 powerpak mlf 9 9
package information vishay siliconix www.vishay.com 2 document num ber: 73386 02-may-05 powerpak mlf 9 9 exposed pad variations (millimeters) d2 e2 d3 e3 min nom max min nom max min nom max min nom max 6.95 7.10 7.25 6.95 7.10 7.25 2.15 2.30 2.45 3.55 3.70 3.85 d4 e4 d5 d6 min nom max min nom max min nom max min nom max 2.75 2.90 3.05 2.85 3.00 3.15 3.65 3.80 3.95 4.25 4.40 4.55 exposed pad variations (inches) d2 e2 d3 e3 min nom max min nom max min nom max min nom max 0.274 0.280 0.285 0.274 0.280 0.285 0.085 0.091 0.096 0.140 0.146 0.152 d4 e4 d5 d6 min nom max min nom max min nom max min nom max 0.108 0.114 0.120 0.112 0.118 0.124 0.144 0.150 0.155 0.167 0.173 0.179 dimensions millimeters* inches dim min nom max min nom max note a ? 0.85 0.90 ? 0.033 0.035 a1 0.00 0.01 0.05 0.000 ? 0.002 11 a2 ? 0.65 0.80 ? 0.026 0.031 a3 0.20 ref 0.008 ref b 0.25 0.30 0.35 0.010 0.012 0.014 4 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc e 0.80 bsc 0.031 bsc e 9.00 bsc 0.354 bsc e1 8.75 bsc 0.344 bsc l 0.50 0.60 0.75 0.020 0.024 0.030 n 32 32 3 nd 8 8 3 ne 8 8 3 p 0.24 0.42 0.60 0.009 0.017 0.024 ? ? 12 ? ? 12 * use millimeters as the primary measurement. ecn: t-05143?rev . a, 02-may-05 dwg: 5948
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
|
